The present invention relates generally to phase locked loops (PLLs), and more specifically to lock detectors used in phase-locked loops.
Phase-Locked Loop Circuits
Phase-locked loop (PLL) circuits are used in many applications, including clock synthesizers, communication circuits, and frequency synchronization, among others. PLL circuits are used to provide an output signal that is phase-locked to an input reference signal. The feedback signal to phase/frequency detector is of the same frequency as the input reference signal.
Conventional PLL circuits typically include a phase/frequency detector (PFD), a charge pump with a loop filter such as a low-pass filter, and a voltage-controlled oscillator (VCO). The PFD is responsive to two signals: the PLL input reference signal, and a feedback signal that is generated from a VCO output signal that is fed back through a divider. When the feedback signal is substantially the same frequency and phase as the input reference signal, then the PLL circuit is “phase-locked.” When the PLL circuit is phase-locked, the two outputs of the PFD, namely, an UP, and a DOWN signal both assume a first logic level indicative of this condition, which may be a logic low level. These signals are used to control the charge pump to increase or decrease its output control voltage VC.
If the input signal leads the feedback signal, indicating that the VCO is running too slow, the PFD produces the pump UP signal (UP) that continues until the rising edge of the feedback signal. Thus, the UP signal may be characterized by a pulse width indicative of the phase difference between the input reference signal, and the feedback signal.
By contrast, if the feedback signal that is input to the PFD leads the input reference signal, the PFD produces a pump DOWN signal that is triggered on the rising edge of the feedback input, and continues until the rising edge of the PLL input reference signal. The DOWN pulse can also be characterized by a pulse width that is indicative of the phase difference between the input reference signal, and the feedback signal.
As a result, the PFD forces the VCO to run faster or slower based on the relationship between the PLL input reference signal, and the feedback signal.
The PLL circuit is characterized by an overall transfer function. Accordingly, before the VCO output locks to the PLL input, a startup interval occurs wherein the feedback signal oscillates about the input reference signal (i.e., undershoots, and overshoots the input reference signal) before a steady state, phase-locked condition is achieved. From an initial power on state of the PLL circuit, thousands and even millions of cycles may be required before this steady state, phase-locked condition is reached.
Lock Detector
In many applications, it is crucial for the system to know at all times whether the system clock, which is usually generated by a PLL, is in lock condition in order to ensure data integrity. Lock-detector circuits can be used for this purpose.
PLL lock detectors are typically used to ensure that a steady-state phase-lock has actually been achieved by the PLL circuit. In many cases, the PLL may appear to be locked when it is not actually locked. For example, during operation of the PLL circuit, the absence of pulses on either the UP or DOWN output terminals of the PFD may appear to be a phase-locked condition, but in reality may be a transitory phase-locked condition that despite lasting several clock cycles is not truly a steady-state phase-lock.
In addition, once the PLL circuit is locked in steady state, it is desirable that detector circuits are immune from minor drifts that can generate pulses on either the UP or DOWN output terminals of the PFD, without discontinuing the logical lock signal.
Of the various lock detector circuits that have been proposed, some require large frequency counters to monitor the frequency of the reference input signal and the signal at the output of the VCO divider. These schemes consume large area of silicon and power, and typically provide only for frequency lock detection, not phase-lock detection. The counters consume significant power because the counters continuously toggle during steady-state locked conditions. Counters can also introduce digital switching noise that can limit the performance of analog components that are used in mixed-signal PLL designs. Further, existing lock-detect circuits typically do not address the failure to lock situation when the reference frequency disappears or deviates significantly from the intended frequency.
Detector circuits have been implemented using pulse discriminators to determine when UP or DOWN pulses of greater than a predetermined pulse width are being generated. Every time the pulse discriminators indicate that wide UP/DOWN pulses have been detected (i.e., indicating that a “near phase-lock” condition has been lost), a free running digital counter is then reset, and the counting process is restarted. However, if the pulse discriminators do not indicate that wide UP/DOWN pulses have been generated before the digital counter counts a preselected number of cycles, the output of the digital counter changes state, which can generate a logical lock signal indicating that a steady state phase-lock has been obtained.
Another approach is to employ a resistor/capacitor (RC) filter responsive to each of the UP and DOWN pulse trains. The respective filters provide a zero pulse output when the phase-locked loop circuit is near phase-lock but provides a non-zero output otherwise. Such an RC filter arrangement is coupled to a corresponding RC charging circuit that is discharged whenever the filtered pulses are non-zero, indicating that the PLL circuit is not locked.
Both of the above-mentioned approaches taken in the art is that each require a large silicon area to implement since digital counters and RC charging circuits are relatively large.
Furthermore, with respect to the RC filter approach, such filters are not typically implemented with a high degree of accuracy. For example, over typical fabrication process variation, the time constant of such RC filters can vary between 10-20%. This variance can directly affect the ability of the lock detector to detect a steady-state phase-locked condition.
Conventional approaches to lock detection suffer from insufficient detection sensitivity with respect to phase error. For example, many lock detectors will output a detection signal when the phase error is as high as 10 picoseconds. However, high performance PLLs require a dead zone of less than 2 picoseconds, and ideally would have zero dead zone. Thus, lock detectors that output a detection signal when the phase error is as high as 10 picoseconds can suffer from precision problems. Moreover, in some lock detectors, the detection sensitivity depends on the frequency of a reference clock or a Voltage Controlled Oscillator (VCO).
Accordingly, there is a need to provide an improved lock detector that reduces or eliminates one or more of the problems set forth above.